`timescale 1ns / 1ps
`include "ExceptStruct.vh"
module IDEXE (
  input         clk,
  input         rst,
  input         stall,
  input         flush,
  input  [63:0] ID_pc,
  input  [31:0] ID_inst,
  input         ID_valid,
  input  [63:0] ID_data1,
  input  [63:0] ID_data2,
  input  [4:0]  ID_rs1,
  input  [4:0]  ID_rs2,
  input  [4:0]  ID_rd,
  input  [63:0] ID_imm,
  input         ID_rs1_use,
  input         ID_rs2_use,
  input         ID_we_reg,
  input         ID_we_mem,
  input  [3:0]  ID_alu_op,
  input  [2:0]  ID_bralu_op,
  input  [1:0]  ID_alu_asel,
  input  [1:0]  ID_alu_bsel,
  input  [1:0]  ID_wb_sel,
  input  [2:0]  ID_data_width,
  input  [63:0] ID_pc_4,
  input         ID_npc_sel,
  input         ID_re_mem,
  input         ID_csr_we,
  input  [63:0] ID_csr_val,
  input         predict_jump_id,
  
  output  reg [63:0] EXE_pc,
  output  reg [31:0] EXE_inst,
  output  reg        EXE_valid,
  output  reg [63:0] EXE_data1,
  output  reg [63:0] EXE_data2,
  output  reg [4:0]  EXE_rs1,
  output  reg [4:0]  EXE_rs2,
  output  reg [4:0]  EXE_rd,
  output  reg [63:0] EXE_imm,
  output  reg        EXE_rs1_use,
  output  reg        EXE_rs2_use,
  output  reg        EXE_we_reg,
  output  reg        EXE_we_mem,
  output  reg [3:0]  EXE_alu_op,
  output  reg [2:0]  EXE_bralu_op,
  output  reg [1:0]  EXE_alu_asel,
  output  reg [1:0]  EXE_alu_bsel,
  output  reg [1:0]  EXE_wb_sel,
  output  reg [2:0]  EXE_data_width,
  output  reg [63:0] EXE_pc_4,
  output  reg        EXE_npc_sel,
  output  reg        EXE_re_mem,
  output  reg        EXE_csr_we,
  output  reg [63:0] EXE_csr_val,
  output  reg        predict_jump_exe
);
import ExceptStruct::ExceptPack;
always @(posedge clk) begin
  if( rst | flush) begin
      EXE_pc <= 0;
      EXE_data1 <= 0;
      EXE_data2 <= 0;
      EXE_inst <= 0;
      EXE_valid <= 0;
      EXE_rs1 <= 0;
      EXE_rs2 <= 0;
      EXE_rd <= 0;
      EXE_imm <= 0;
      EXE_rs1_use <= 0;
      EXE_rs2_use <= 0;
      EXE_we_reg <= 0;
      EXE_we_mem <= 0;
      EXE_alu_op <= 0;
      EXE_bralu_op <= 0;
      EXE_alu_asel <=0;
      EXE_alu_bsel <= 0;
      EXE_wb_sel <= 0;
      EXE_data_width <= 0;
      EXE_pc_4 <= 0;
      EXE_npc_sel <= 0;
      EXE_re_mem <= 0;
      EXE_csr_we <= 0;
      EXE_csr_val <= 0;
      predict_jump_exe<=0;
  end
  else if(~stall) begin
      EXE_pc <= ID_pc;
      EXE_data1 <= ID_data1;
      EXE_data2 <= ID_data2;
      EXE_inst <= ID_inst;
      EXE_valid <= ID_valid;
      EXE_rs1 <= ID_rs1;
      EXE_rs2 <= ID_rs2;
      EXE_rd <= ID_rd;
      EXE_imm <= ID_imm;
      EXE_rs1_use <= ID_rs1_use;
      EXE_rs2_use <= ID_rs2_use;
      EXE_we_reg <= ID_we_reg;
      EXE_we_mem <= ID_we_mem;
      EXE_alu_op <= ID_alu_op;
      EXE_bralu_op <= ID_bralu_op;
      EXE_alu_asel <=ID_alu_asel;
      EXE_alu_bsel <= ID_alu_bsel;
      EXE_wb_sel <= ID_wb_sel;
      EXE_data_width <= ID_data_width;
      EXE_pc_4 <= ID_pc_4;
      EXE_npc_sel <= ID_npc_sel;
      EXE_re_mem <= ID_re_mem;
      EXE_csr_we <= ID_csr_we;
      EXE_csr_val <= ID_csr_val;
      predict_jump_exe <= predict_jump_id;
  end

end
endmodule